Efficient Implementation of AES and CTR_DRBG on 8-Bit AVR-Based Sensor Nodes

Since Rijndael algorithm was selected as the Advanced Encryption Standard (AES) by NIST, optimization research for AES has been actively conducted on various IoT-based processors. In an 8-bit AVR environment, LIGHT version of Fast CTR-mode (FACE-LIGHT) proposed at ICISC'2019 conference. However, in a Wireless Sensor Network where sessions are frequently changed, FACE-LIGHT seems not efficient terms available memory and generating pre-computation table. this article, we present new column-wise fashion implementation. Unlike previous best implementations, our implementation microcontroller combines SubBytes, ShiftRows, MixColums operations optimizes operation speed through register scheduling. Our constant-time uses significantly less table than microcontroller, achieving 2,251, 2,706, 3,160 clock cycles when encrypting 128-bit data each three security levels. particular, 256-bit level is fastest far know microcontroller. Finally, apply CounTeR-mode_Deterministic Random Bit Generator (CTR_DRBG), one upper algorithms symmetric-key algorithm, to prove generality technology operating modes AES.